The Test Attributes of Controllability and Observability

If a tree falls in a forest with no one around to hear it, does it still make a sound?

If a fault occurs in a combinational circuit but its masked at the outputs is it still a fault?

If you can’t excite a fault from the circuit inputs does it really exist?

If you can’t propagate a fault to an output pin, does it matter?

In assessing an integrated circuit’s testability engineers consider the concepts of controllability and observability. In these specific characteristics of testability came up often the academic test literature of the 1970’s and 1980’s. The challenge back then was automatic test generation and fault simulation.

Concepts

I’ll use the definitions provided by Abramovici, Breuer and Friedman in their book “Digital Systems Testing and Testable Design.” From Chapter 9, Design for Testability:

Controllability: ability to establish a specific signal value at each node in a circuit from setting values at the circuit’s inputs.

Observability: ability to determine the signal value at any node in a circuit by controlling the circuit’s inputs and observing its outputs.

A circuit’s design impacts a circuit’s controllability and observability. These attributes impact an algorithm’s for generating tests (a subject for future articles). Test generation costs less for circuits with better controllability and observability. Design For Test (DFT) techniques improve these attributes which lead to increased fault coverage, decreased test generation costs and often decreased test time.

Often techniques address both controllability and observability. Though let’s start alphabetically with controllability.

Controllability Techniques

Recall in How to Test Clocked Circuits that you needed an ability to set the initial state. That’s a controllability need.

One way to do it is at power-on initialize the latch/flip-flop to an initial state. That’s partial solution.  You can only choose one state.  For complete controllability you need to be able to set the value to 0 and a 1. You can then have two ways of setting the latches:  A clear- set all to a 0 and a pre-set to an initial value.  Designers may add such features, as they too want some predictability in how the circuit will behave. However, a designer when presetting a values has a mission/functional mode in mind.  For test purposes you need more control.

An ad-hoc technique to increase controllability is adding a test point- adding a signal that you can control externally.

For larger circuits you can divide and conquer. Consider a counter, these can be difficult to test because of all the clock cycles to go through all the states. A 16-bit counter takes 65536 cycles, split that into two 8-bit counters and you get 256 cycles per partition. Test them in parallel and you have halved the test time.

Scan Based design increases both controllability and observability. You are able to set internal states and observe internal states. Full Scan design means all latches/flip-flops are part of the scan chain. Partial scan design means you are selective in the latches/flip-flops that become part of the scan chain.

Observability Techniques

Any technique which enhances your ability to observe a particular state counts. Turns out most of the controllability techniques double as an observability technique.

Adding a test point which connects an internal state to an external pin provides additional observability. This can become expensive in terms of output pins.  You can trade-off area and time by using a scan register to capture internal node values and connect this to an external pin. You can do the same for controlling a node values with a scan-register controlled by a test point.

DFT Tradeoffs When Increasing Controllability and Observability

Like all engineering tasks generating tests to cover all IC faults involves trade-offs. You may have noticed that improving controllability and observability techniques costs additional hardware (pins, interconnect or circuits). The benefit is typically shorter computation of tests generated, higher test quality for less test patterns. There are also collateral benefits- increased observability makes it easier for you to do fault isolation and then you need to do.

You can mitigate some of the costs. Which hardware cost have you seen as the most to be used?

Meanwhile remember testing takes time and thoughtful application,

Anne Meixner, PhD

Additional Reading:

If you like philosophical discussions of the “If the tree falls….” I found this to be a light personal thread on the Guardian. If you want to go deeper check out the Wikipedia articleWikipedia article.

Abramovici, Breuer and Friedman’s book “Digital Systems Testing and Testable Design” available on Amazon.

Abramovici et al also describe another term which I have not often heard used in my professional circles but I believe upon reading makes sense to raise to your awareness as it captures all the other subtle things that can impact the ability to test a circuit:

Predictability: ability to obtain knowns output values in response to given input stimuli.

Factors that affect predictability should be red flags to anyone dealing with electronics repeatability and reliability: Initial state of a circuit, races, hazards and free-running oscillators.